AMD vs. Intel and Nvidia - The Next-Gen GPU War is ON!

[Irvrobinson]

Actually they are. AMD handles caches differently than the ring bus architecture. The way AMD is secure is due to their architecture. Intel noted the possibility using the ring bus architecture of the side channel attacks back in the late 90’s and ignored the finding. Intel doesn’t secure the cache hoping ring permissions would be enough. It was not. Now they have a mess due to lack of development of a much more secure processor needed to stop the side channel attacks of which there is a plethora of now.

You don't seem to have any idea what you're talking about, so I don't think this discussion is productive. You're mixing multiple concepts in a single sentence that aren't architecturally related. Side channel attacks are based on the physical attributes of the processor, like power consumption monitoring, among other things. Intel CPUs have numerous security vulnerabilities, but a lot of them are due to SGX itself not being secure, and your fixation on Ring-Bus shows you don't understand how CPUs work.

 

[stalag2005]

Okay, I am at a real keyboard. Yes I understand Intel CPU's, my research as a graduate student depended on their architecture. Suffice the ring bus has 3 levels of execution. Rings one and two are relatively unimportant, but ring zero is privileged kernel space on the processor and ring three is user space. Ring three is where the processor receives requests for the processor time and the kernel organizes and schedules the processor compute request in ring zero. Anything that penetrates and exposes ring zero data which is where the cache ram and the processes that load and move the data to the processors occurs, is a thing that one should never happen. The fact that there are multiple vectors of attack, bluntly no data from a cache should EVER be exposed. I am not going into the minutia of detail here, just suffice to say that Intel IMHO has these exposures on such a regular basis that leads me to say they need to redesign their processors. I really don't care if it is through SGX, power changes, or any other method, the result is the same, exposure of the data. Linus Torvalds here said that Intel's attempts to patch meltdown and spectre were crap, and all the subsequent exposures of cache IMHO are symptoms of the same problem, an aging architecture that badly needs a redesign to fix the numerous flaws leading to exposure of cache data. Patches in software might mitigate, but still does not fix everything. And very few people ever update their bios like they should nor do they ever update the driver kit that might mitigate. But the only true fix would be a ground up redesign.

 

[Irvrobinson]

Okay, I am at a real keyboard. Yes I understand Intel CPU's, my research as a graduate student depended on their architecture. Suffice the ring bus has 3 levels of execution. Rings one and two are relatively unimportant, but ring zero is privileged kernel space on the processor and ring three is user space. Ring three is where the processor receives requests for the processor time and the kernel organizes and schedules the processor compute request in ring zero. Anything that penetrates and exposes ring zero data which is where the cache ram and the processes that load and move the data to the processors occurs, is a thing that one should never happen. The fact that there are multiple vectors of attack, bluntly no data from a cache should EVER be exposed. I am not going into the minutia of detail here, just suffice to say that Intel IMHO has these exposures on such a regular basis that leads me to say they need to redesign their processors. I really don't care if it is through SGX, power changes, or any other method, the result is the same, exposure of the data. Linus Torvalds here said that Intel's attempts to patch meltdown and spectre were crap, and all the subsequent exposures of cache IMHO are symptoms of the same problem, an aging architecture that badly needs a redesign to fix the numerous flaws leading to exposure of cache data. Patches in software might mitigate, but still does not fix everything. And very few people ever update their bios like they should nor do they ever update the driver kit that might mitigate. But the only true fix would be a ground up redesign.

I've already pointed out that you are confusing the Ring-Bus, which is an on-die interconnect between cores and memory controllers, and Protection Rings, which define execution state privilege levels allowing access to memory regions in user or kernel space(s). You are correct that the Meltdown issue (as an example) is worse for Intel because the speculative execution functionality in out of order execution logic has higher privilege level access than, say AMD, which gives their equivalent functional units access only to user-mode privilege. However, this has nothing to do with the Ring-Bus architecture, and everything to do with OOO execution and protection rings.

 

[stalag2005]

Okay, still the interconnects have to operate in ring zero. They are still vulnerable due to the nature of the protection ring they operate in. Even if I am mixing them a little, the fact that it is all in a protection ring of privileged access that has been breached in multiple ways. Even if Intel keeps the interconnect, they still need to harden the protection rings. If it means a redesign of the interconnect, they still need the redesign.

 

[Irvrobinson]

Okay, still the interconnects have to operate in ring zero. They are still vulnerable due to the nature of the protection ring they operate in. Even if I am mixing them a little, the fact that it is all in a protection ring of privileged access that has been breached in multiple ways. Even if Intel keeps the interconnect, they still need to harden the protection rings. If it means a redesign of the interconnect, they still need the redesign.

I'd like to preface my response by saying that my comments should not be construed as an endorsement of Intel's use of a ring topology for a coherent on-die interconnect, nor as a defense of Intel's CPU engineering WRT to security. Ring topology coherent interconnects have been displaced by superior 2D-mesh interconnects in Intel Xeons, AMD EPYCs, and ARM multi-core and SoC designs. Intel CPUs have been shown to have more security vulnerabilities than AMD, partially due to the before-mentioned OOO execution design decisions, and Intel is also trailing AMD in the implementation of memory-controller-based DRAM encryption, to name another issue in a list of them (SGX versus SME/TSME). It is clear that Intel did not prioritize security in their product management process, though I wonder if some of these vulnerabilities seem to mostly impact public cloud computing and server CPUs, and may have little or no impact on PCs and laptops with client CPUs. Some of the side-channel attack descriptions also stretch credibility in real-world implementation, and some seem more like good fodder for academic publishing than practical threats. (I don't really know, I'm just wondering out loud.)

I am surprised that you have doubled down on your incorrect analysis and unsupported assertions about Intel's security issues. A coherent interconnect like Ring-Bus does not operate in a protection ring, it operates architecturally below them, simply transmitting 64 byte cache lines which refer to physical memory addresses. CPU protection domains operate on virtual memory addresses. The OOO execution in OS and VMM privileged regions is not indicative of the need to harden protection rings, it is just an artifact of the speculative execution designs. One reason the OOO/speculative execution functionality is able to cause problems because (like coherency protocols) they are likewise implemented in hardware and function architecturally below and transparently to the OS or VMM executing in the virtual memory domain. Another example of functionality that works at the physical memory address level are DMA (Direct Memory Access) engines, which are commonly used by networking and storage adapters.

This is a reasonably well-written five year-old article from Intel's website on how caches work, the difference between interconnect rings and 2D meshes, and the relationship between virtual and physical addressing. Note that this is an old article, so the Phi CPU has been cancelled, and now Xeons use a similar 2D mesh.

How Memory Is Accessed

This article explains why optimal usage of the memory subsystem can have massive performance benefits

software.intel.com

 

[pcosmic]

So how do you clean moldy caulk?

Best there is, best there was, best that ever will be. Spray it and run away for an hour. Come back and wipe it down.

Mold Armor 32 oz. Mold and Mildew Killer and Quick Stain Remover FG502 - The Home Depot

Mold Armor Instant Mold and Mildew Stain Remover are suitable for toilet, fiberglass and shower doors. Convenient to spray.

www.homedepot.com

 

[Irvrobinson]

Best there is, best there was, best that ever will be.

A line right out of the movie The Natural. Of course in that movie, that description by reporter Max Mercy of The Whammer was proven to be incorrect.

 

[davidscott]

Or the catchphrase of WWE wrestler Brett Hart in the mid 90s.

 

[Irvrobinson]

Or the catchphrase of WWE wrestler Brett Hart in the mid 90s.

It's sort of frightening that you know that...

 

[davidscott]

It's sort of frightening that you know that...

Been watching WWE off and on for a long time. Not sports but sports entertainment. Never been to a live show so maybe I'm not too far gone.

 

[davidscott]

Back on topic are we close to integrated graphics being enough for mid high level gaming?

 

[NINaudio]

Back on topic are we close to integrated graphics being enough for mid high level gaming?

Nope

 

[panteragstk]

AMD is the closest for APU graphics, but still nowhere near a dedicated GPU. Even a lower end one can easily beat anything integrated.

I'm a big fan of just keeping integrated graphics out of the CPU (depending on the lineup) and free up space on the die for more important things like PCIe lanes.

 

[BoredSysAdmin]

AMD is the closest for APU graphics, but still nowhere near a dedicated GPU. Even a lower end one can easily beat anything integrated.

I'm a big fan of just keeping integrated graphics out of the CPU (depending on the lineup) and free up space on the die for more important things like PCIe lanes.

Early M1 numbers on GFX look promising, and while still far from what I'd call a comfortable 1080p 60fps gaming,
it (M1 Gpu) already exchanging blows with low to low-middle GPUs like 1050ti and RX560

Apple’s M1 chip can apparently outperform some AMD and Nvidia graphics cards

All that on a chip?

www.techradar.com

.

I think we are still a full generation or likely two before we get a comfortable 1080p 60fps AAA title gaming on a SOC.

 

[panteragstk]

Early M1 numbers on GFX look promising, and while still far from what I'd call a comfortable 1080p 60fps gaming,
it (M1 Gpu) already exchanging blows with low to low-middle GPUs like 1050ti and RX560
View attachment 42198

Apple’s M1 chip can apparently outperform some AMD and Nvidia graphics cards

All that on a chip?

www.techradar.com

.

I think we are still a full generation or likely two before we get a comfortable 1080p 60fps AAA title gaming on a SOC.

Good point. Apple threw a wrench into everything for sure. It'll be very interesting to see what AMD, nvidia, and Intel can come up with to go against the M1 in the next few years.